1. Field of the Invention
The invention relates to telecommunications. More particularly, the invention relates to methods and apparatus for desynchronizing a DS-3 signal and/or an E3 signal from the data portion of an STS/STM payload.
2. State of the Art
Since the early nineteen sixties, three different digital multiplexing and signalling hierarchies have evolved throughout the world. The hierarchies were developed in Europe, Japan, and North America. Fortunately, all are based on the same pulse code modulation (PCM) signalling rate of 8,000 samples per second, yielding 125 microsecond sampling slots (1 second/8,000 samples=0.000125). Japan and North America base their multiplexing hierarchies on the DS-1 rate of 1.544 Mbit/secxc2x120 ppm, although the higher data rates in Japan do not correspond to the higher rates used in North America. Europe bases multiplexing on a rate of 2.048 Mbits/sec called E1 which carries thirty voice circuits compared to the twenty-four carried in the DS-1 rate. The next most common higher rates in the U.S. and Europe are DS-3 and E3, respectively, which have rates of 44.736 Mbit/secxc2x120 ppm and 34.368 Mbit/secxc2x120 ppm, respectively.
The Synchronous Optical Network (SONET) or the Synchronous Digital Hierarchy (SDH), as it is known in Europe, is a common transport scheme which is designed to accommodate both DS-1 and E-1 traffic as well as multiples (DS-3 and E3) thereof. Developed in the early 1980s, SONET has a base (STS-1) rate of 51.84 Mbit/sec in North America. In Europe, the base (STM-1) rate is 155.520 Mbit/sec, equivalent to the North American STS-3 rate (3*51.84=155.520). The abbreviation STS stands for Synchronous Transport Signal and the abbreviation STM stands for Synchronous Transport Module. STS-n signals are also referred to as Optical Carrier (OC-n) signals when transported optically rather than electrically.
Prior art FIGS. 1 and 2 illustrate the basic STS-1 signal which has a frame length of 125 microseconds (8,000 frames per second) and is organized as a frame of 810 octets (9 rows by 90 byte-wide columns). It will be appreciated that 8,000 frames*810 octets per frame*8 bits per octet=51.84 Mbit/sec. The first three columns of each row consist of transport overhead (TOH). Of these twenty-seven octets, nine are allocated for section overhead and eighteen are allocated for line overhead. The remainder of the frame (9 rows of 87 columns=783 octets) is referred to as the envelope or Synchronous Payload Envelope (SPE) or, in Europe, the Virtual Container. The first column of the envelope is reserved for STS path overhead (POH) and is referred to as the transport part of the envelope. The remaining 86 columns is referred to as the user part of the envelope. The difference between path overhead, line overhead, and section overhead is illustrated by FIG. 3. Path represents the complete transit through the SONET network. Line represents transit from one multiplexer to another. Section represents transit from one network element to another.
In order for data to be accommodated efficiently in the SPE, the 87 bytes of the SPE are divided into three blocks each including 29 columns. The POH occupies column 1 and xe2x80x9cfixed stuffxe2x80x9d (bytes which convey no information) is inserted into the 30th and 59th columns. Data is accommodated in the remaining 3*28=84 columns=756 bytes. An STS-n signal is n STS-1 signals which are frame aligned and byte-interleaved. Currently, the highest level STS signal is STS-192 which has a line rate of 9,953.28 Mbit/sec.
These various synchronous optical network signals contain payload pointers (prior art FIG. 2) which provide a method of allowing flexible and dynamic alignment of the SPE (Virtual Container) within the envelope or container capacity, independent of the actual contents of the envelope or container. Dynamic alignment means that the STS or STM respective SPE or Virtual Container is allowed to float within the STS/Virtual Container envelope capacity/container. For example, as shown in prior art FIG. 4, STS-1 SPE may begin anywhere in the STS-1 envelope capacity. Typically, it will begin in one STS-1 frame and end in the next frame as shown in prior art FIG. 4. The STS payload pointer is contained in the H1 and H2 bytes (the first two bytes) of the line overhead (prior art FIG. 2). These two bytes designate the location of the payload byte (the J1 byte) where the STS SPE begins.
When first generated, an SPE is aligned with the line overhead at the originating node (i.e., the pointer value is 0). As the frame is carried through a network, however, it arrives at intermediate nodes (e.g., multiplexers or cross-connects) having an arbitrary phase with respect to the outgoing transport framing of the intermediate nodes. If the SPE had to be frame-aligned with the outgoing signal, the frame would need to be buffered and delayed. Thus, the avoidance of frame alignment allows SPEs on incoming links to be immediately relayed to outgoing links without artificial delay. The location of the SPE in the outgoing payload envelope is specified by setting the H1, H2 pointer to the proper value (0-782). The pointer values are reset at each intermediate node in the network.
In addition, if there is a frequency offset between the frame rate of the transport overhead and that of the STS SPE, then the pointer value will be incremented or decremented, as needed, accompanied by a corresponding positive or negative stuff byte. If the frame rate of the STS SPE is too slow with respect to the transport overhead, then the alignment of the envelope must periodically slip back in time, and the pointer must be incremented by one. This operation is indicated by inverting selected odd bits (I-bits) of the pointer word to allow five-bit majority voting at the receiver. A positive stuff byte appears immediately after the H3 byte in the frame containing inverted I-bits. Subsequent pointers will contain the new offset value. Consecutive pointer operations must be separated by at least three frames in which the pointer value remains constant. This implies a very wide tolerance of clock accuracy required for maintaining SPE data, i.e., xc2x1320 ppm. In comparison, a SONET node is specified to maintain a minimum timing accuracy of xc2x120 ppm if it loses its reference.
If the frame rate of the STS SPE is too fast with respect to that of the transport overhead, then the alignment of the envelope must be periodically advanced in time, and the pointer must be decremented by 1. This operation is indicated by inverting selected even bits (D-bits) of the pointer word to allow five-bit majority voting at the receiver. A negative stuff byte appears in the H3 byte in the frame containing the inverted D-bits. Subsequent pointers will contain the new offset value.
Both the SONET and SDH standards define a mechanism for mapping the DS-3 or E3 signal into the SONET/SDH payload. For DS-3, positive bit stuffing is defined in which each of the nine rows contain 622 bit positions, including one bit which may be data or stuff. A frequency of 44.736 MHz is achieved if one-third of the rows contain 621 information bits and one stuff bit, and two-thirds of the rows contain 622 information bits and no stuff bits. For E3, a positive-zero-negative mapping mechanism is used, with two stuff opportunities per every three rows. Two rows of 477 bits and one row of 478 bits transport a 34.386 MHz signal. Adding one extra data or one extra stuff allows transported frequency flexibility.
Thus, it will be appreciated that a SONET/SDH signal which carries a DS-3 or an E3 signal will contain overhead bytes, stuff bytes, and other control information. When the DS-3 or E3 signal is extracted from the SONET/SDH signal, these additional bytes must be stripped out, thereby producing gaps in the 51.84 MHz clock of the extracted signal. This xe2x80x9cgappedxe2x80x9d DS-3 or E3 must be reconstituted into a slower (44.736 MHz or 34.368 MHz, respectively) signal having no gaps. This process is generally referred to as xe2x80x9cdesynchronizingxe2x80x9d.
One state-of-the-art device which, among other things, desynchronizes DS-3 and/or E3 signals which have been extracted from a SONET/SDH signal is the Transwitch(copyright) L3M(trademark) (level 3 mapper) device. The L3M(trademark) device includes a desynchronizer having two parts: a pointer leak circuit and a phase-locked loop circuit. The pointer leak circuit absorbs the immediate effect of up to eight consecutive pointer movements (any combination of SPE or TUG-3 pointer movements) in either direction, and filters them out over time. A single pointer adjustment is an 8 Unit Interval (UI) phase step. The pointer leak circuit turns the phase step into eight 1-UI steps, widely spaced in time, allowing the phase-locked loop circuit to track. In normal operation, the output is one data bit and one clock cycle for each input bit. When a negative stuff occurs, eight extra bits are pulled from the signal and absorbed. Following this operation, the normal operation of one bit in for one bit out continues except that one extra bit is pulled from the FIFO every n frames. In this way, the pointer step is leaked out in 8 n frames, the value of n being programmable. The phase-locked loop circuit of the desynchronizer is externally connected to a line-frequency voltage controlled crystal oscillator (VCXO) via an external filter. This arrangement is designed to meet limits for jitter on the asynchronous line output signal, which is due to signal mapping and pointer movements.
The state-of-the-art desynchronizer has several disadvantages. For example, it requires an external VCXO and the pointer leak rate must be calculated by an external processor.
It is therefore an object of the invention to provide methods and apparatus for desynchronizing a DS-3/E3 signal from the data portion of a SONET/SDH signal.
It is also an object of the invention to provide desynchronizing methods and apparatus which do not require an external oscillator.
It is another object of the invention to provide desynchronizing methods and apparatus which do not require external logic to calculate a pointer leak rate.
It is a further object of the invention to provide a completely internal desynchronizer which meets all network requirements, e.g. regarding jitter and wander.
Another object of the invention is to provide a desynchronizer circuit which uses less chip and board space and is more cost effective.
In accord with these objects which will be discussed in detail below, the desynchronizer of the present invention includes three sections: a leak and spacing function section, a digitally-controlled oscillator (DCO) based closed loop section, and an analog output section. The first two sections include a first FIFO that is shared in a specific manner. The FIFO includes a RAM and two counters. A write counter provides the incoming bit write address, and is indexed on every bit entered into the FIFO. A read counter provides the address of the bit to be read out, and is indexed on the DCO clock. An intermediate count (or location) calculation is indexed synchronously with the received SONET/SDH frame phase (on a row basis or otherwise), and defines the boundary (location) between two parts of the FIFO; i.e., the leak spacing section of the FIFO and the DCO-based closed loop section of the FIFO. Length measurements of both FIFO parts and the calculation of the intermediate count are synchronously made with the received SONET/SDH frame phase (preferably on a row basis). The combination of the synchronicity of the two measurements and the calculation, together with the size of the increments, as described below, significantly reduce the phase noise impact of the SONET/SDH overhead.
The first two sections provide the third section with a DS-3/E3 signal having a high frequency phase modulation of known characteristics. Substantially all of the low frequency components, including SONET/SDH systemic gapping are removed by the first two sections. The third section is a smoothing stage which includes a PLL having a second FIFO with read and write counters, a phase-frequency detector, and an internal analog VCO controlled by length measurements of the second FIFO. The second stage substantially removes the remaining high frequency gapping jitter (approximately 3.42 MHz). According to the presently preferred embodiment, a fixed frequency of 51.84 MHz is derived from the 19.44 MHz STS-3 or STM-1 clock through 8 x multiplication and /3 division. The first FIFO is preferably a 768-bit RAM, and the two counters (write and read) are preferably each ten bits long. Data is entered into the first FIFO from a SONET/SDH de-mapper which strips away all of the SONET/SDH overhead as well as any bits in the payload which do not represent DS-3/E3 data. As such, data enters the FIFO on a gapped 51.84 MHz clock, with the gaps representing missing clock pulses during which no data enters the FIFO. This inlet clock which is gapped is used to index the write counter as well as a pointer leak control and spacing function. The read counter, on the other hand, is indexed on a DCO gapped clock (the gapping being high frequency in nature). The DCO gapped clock is derived from the 51.84 MHz input gapped clock via a closed loop spacing circuit which uses the intermediate count calculation and the read counter. The intermediate count preferably is calculated synchronously with the SONET/SDH row time. More particularly, the intermediate count is incremented in one manner for a DS-3 signal and in another manner for an E3 signal. In the case of a DS-3 signal, the exact frequency of 44.736 MHz is produced when three rows of a SONET frame contain one row of 621 data bits and two rows of 622 data bits. This bit rate is achieved by incrementing the intermediate count according to a schedule which also takes into account pointer leaks and stuffs. In the case of an E3 signal, the exact frequency of 34.368 MHz is produced when three rows of a SONET frame contain one row of 478 data bits and two rows of 477 data bits. This bit rate is achieved by incrementing the intermediate count according to a schedule which also takes into account pointer leaks and stuffs.
The DCO generates the DCO gapped clock from the 51.84 MHz clock and from a loop control signal. The DCO nominally produces ten or eleven output pulses per sixteen pulses of the 51.84 MHz clock in the case of an E3 signal and thirteen or fourteen output pulses per sixteen pulses of the 51.84 MHz clock in the case of a DS-3 signal to produce the outlet gapped clock which will track the source E3 or DS-3 frequency. The exact ratio of pulses is adjusted based on the difference (mod-256) between the intermediate count and the read counter count. More particularly, the difference between the read count and the intermediate count is read periodically and averaged every eight measurements. The average is expressed as a ten bit number which is added to a twenty-three bit offset to produce the loop control signal. The twenty-three bit loop control word is supplied to a twenty-three bit accumulator and twenty-three bit latch. The accumulator outputs a twenty-three bit sum and a carry. The latch stores the sum and the carry is stored in a flip-flop. Every time the DCO counter cycles through sixteen pulses of the 51.84 MHz clock, the accumulator performs a twenty-three bit add of the new control word with the contents of the latch. The frequency of the carries depends on the value of the control word. When the carry is active, the pulse detection control passes the lower number of pulses per sixteen DCO clock pulses, i.e. thirteen for DS-3, ten for E3. This converts the 51.84 MHz clock to the DCO gapped clock which is used to read data from the first stage FIFO.
The write counter count and the intermediate count are also used to enable pointer bit leaks. The leak spacing is based on the observed pointer movements over time as well as on the length of the first section of the FIFO which is given by the difference between the write counter and the intermediate count. If the length of the first part of the FIFO deviates beyond a nominal length value, pointer leaks are enabled more frequently (negative if the length is smaller than the offset, positive if the length is larger than the offset).
The third stage of the desynchronizer of the invention includes a second FIFO which receives data from the second section of the first FIFO according to the DCO gapped outlet clock, associated write and read counters, and an analog portion. The analog portion includes a phase-frequency detector (PFD), a low pass filter, and an analog VCO. The MSB of the read counter and write counter of the second FIFO (which is preferably a 64-bit RAM) are inputs to the PFD. The Up and Down outputs of the PFD are summed by the low pass filter and the sum is used to control the internal analog VCO which is used to clock data out of the second FIFO and hence out of the desynchronizer.
Additional objects and advantages of the invention will become apparent to those skilled in the art upon reference to the detailed description taken in conjunction with the provided figures.